1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having hierarchically structured bit lines. Furthermore, the present invention relates to a system including the semiconductor device.
2. Description of Related Art
Some semiconductor devices such as DRAM (Dynamic Random Access Memory) include local bit lines and global bit lines that are hierarchically structured (see U.S. Pat. No. 5,682,343). The local bit line corresponds to a low-order bit and is connected to a memory cell. On the other hand, the global bit line corresponds to a high-order bit and is connected to a sense amplifier. With hierarchized bit lines, it is possible to increase the number of memory cells allocated to one sense amplifier, while shortening a line length of the local bit line that has a relatively high electrical resistance.
In a semiconductor device described in U.S. Pat. No. 5,682,343, adopts so-called open bit architecture. That is, a pair of global bit lines connected to a sense amplifier is allocated to different memory mats from each other. As is widely known, unlike a folded bit line architecture, because word line noise is not canceled in the open bit architecture, the word line noise is superimposed on a bit line of an access side. To deal with this problem, as shown in FIGS. 18 and 19 of U.S. Pat. No. 5,682,343, a dummy word line is used to cancel word line noise.
However, in the semiconductor device described in the above patent document, although word line noise can be canceled, it is not possible to deal with a difference in a parasitic CR distributed constant based on a position of a selected local bit line. Because a plurality of bit lines are allocated to one global bit line, a slight difference occurs in the parasitic CR distributed constant between a case where a local bit line near a sense amplifier is selected and a case where a local bit line far from the sense amplifier is selected. In the semiconductor device described in the above patent document, because a memory mat provided with the dummy word line is fixed, the sensing sensitivity degrades due to a difference in the parasitic CR distributed constant caused by the position of the selected local bit line.
Meanwhile, in recent years, a 4 F2 memory cell has been developed. In a typical 4 F2 memory cell, because the bit line is embedded in a semiconductor substrate, the word line noise is considerably small. In this type of semiconductor device, an influence of a change of the parasitic CR distributed constant caused by the position of the selected local bit line is rather dominant than an influence of the word line noise. Therefore, in this case, there is little necessity of using the dummy word line.